The embodiments of the inventive concept are directed to detection of a lock state of a phase-locked loop (PLL) circuit, and more particularly, to a lock detection circuit and a PLL circuit including the lock detection circuit.
Phase-locked loop (PLL) circuits are widely used in communications, multimedia, and other applications, such as, for example, frequency synthesizers, FM demodulators, block recovery circuits, modems, and tone decoders.
A PLL circuit includes a lock detection circuit capable of detecting a lock state. However, as a bias voltage used in the lock detection circuit varies depending on changes in process-voltage-temperature (PVT) parameters and other greatly fluctuating parameters, a delay time changes together with the bias voltage. Thus, the lock detection circuit cannot accurately detect a lock state in the PLL circuit.